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MX-3204 · 6310i · 6101 · 6111 · 6300 · 5300 · W380 · Rumor 2

A Framework for Stochastic Differentiable Programming

Guillaume Verdon, Leo Tyrpak, Owen Lockwood, Seth Morton, Alexander Neagoe, Anton Sugolov, Ian MacCormack, Mirko Amico · arXiv:2608.01612 · 3 August 2026 (v2, 13 August) · the torx paper

Parametrized Stochastic Circuits — a random program written as a circuit. Three kinds of wire carry the values: a pbit (two states), a pdit (d states) and a pmode (a continuous number). Instead of a wire holding a value, it holds a whole probability distribution over values, and a gate reshapes that distribution.

Small and physical. PNOT flips a pbit with probability p; PSWAP exchanges two pbits; PIsing is the two-spin magnet interaction. On the continuous side, an affine Gaussian gate and an Ornstein-Uhlenbeck gate. Hybrid gates let a discrete wire steer a continuous one.

Three methods, with an honest ranking. REINFORCE works on any gate and is unbiased but noisy. A parameter-shift rule gives lower-variance gradients but only for one family of gates, and costs a separate run of the circuit per parameter. Energy-based gates get their own gradient rule needing one extra sample each.

An 8-site Ising ring — small enough that all 256 states can be enumerated exactly, so there is a known right answer. They drew 20,000 samples on the physical X0 chip and used them as the randomness for Metropolis-Hastings and importance sampling. The resulting distribution was as close to the exact answer as NumPy’s pseudorandom generator managed. Only the source of randomness changed; the program did not.

Measured on X0: hundreds of attojoules to a few femtojoules per sample at 10–50 MHz. Calibration is per-device, by Bayesian optimisation, landing within about 5% absolute probability error.

Random walks on graphs; discrete diffusion on binarised MNIST (bit-error rate 0.114 → 0.113, closing 41% of the FID gap to clean data); a graph network trained to find a maximum cut (it recovered the optimal cut of 12 in most runs); a three-regime jump-diffusion model; and Ising sampling, where the chromatic layout scored a TV distance of 0.052 against 0.402 for the naive edge-by-edge layout — nearly 8× worse.

Its own words: the demonstrations are sized to showcase capabilities rather than show an efficiency advantage. This paper makes no scalability or speed claim at all. It is a programming model plus a proof that hardware randomness is usable.

Thermalizing Stochastic Programs

Mirko Amico, Andraž Jelinčič, Colin Oscar Nancarrow, Leo Tyrpak, David Roberts, Seth Morton, Dalton Sakthivadivel, Ashwin Gopal, Guillaume Verdon · arXiv:2608.01615 · 3 August 2026 (v2, 13 August) · the compiler paper

You have written a random program in torx. The chip does not speak that language — it only knows how to settle into low-energy states. Something has to translate.

Take each step of the program on its own. Clamp its inputs, let the hidden and output nodes thermalise by Gibbs sampling, and read what comes out. Tune the chip’s weights until that output matches what the step was supposed to do — formally, minimise the KL divergence between the two. Repeat for every step, then wire them back together.

Compiling each piece separately should be a disaster: errors ought to pile up as the program gets longer. The paper proves the total error is bounded by the sum of the per-step errors — and, crucially, that for mixing (contracting) steps the error saturates at a floor that does not grow with depth. A long program is not doomed. That bound is the paper’s real contribution.

Context matching: train each step on the inputs it will actually receive from the compiled step before it, not on idealised inputs. Trajectory-level REINFORCE: after compiling, tune every step jointly against how the whole program performs. On a biased random walk over a 5×5 torus, context matching cut the error roughly 10×, and REINFORCE post-training cut it roughly 10× again — restoring a conservation law that naive compilation had broken.

A market simulator that learns day-to-day equity co-movements from recorded history alone, using one weight-tied kernel applied over and over — structurally the same trick a language model uses. A birth-death model from ecology, compiled in closed form with no gradient descent at all. A three-body Ising interaction the hardware cannot natively express, reached anyway through compiled conditionals. And a Gaussian circuit driving a sequential Bayesian experimental design loop.

Every experiment here runs on a software simulation of Z1, not on silicon — modelled as ~250,000 nodes on a planar grid, degree-16, at roughly 3×10⁻¹⁰ J per Gibbs iteration. Stated limits: couplings must be symmetric, REINFORCE is high-variance and needs a good starting point, sharpening a step makes it mix more slowly (which biases the gradients), and continuous values must be discretised.

An efficient probabilistic hardware architecture for diffusion-like models

Andraž Jelinčič, Owen Lockwood, Akhil Garlapati, Peter Schillinger, Isaac Chuang, Guillaume Verdon, Trevor McCourt · arXiv:2510.23972 · 28 October 2025 (v2, 10 December) · the 10,000× paper

A system-level analysis indicating that devices built on this architecture could achieve performance parity with GPUs on a simple image benchmark using approximately 10,000 times less energy. Note the grammar: could, system-level analysis, simple image benchmark. The paper is careful even if the internet quoting it is not.

Because of the mixing-expressivity tradeoff: make one energy landscape rich enough to describe real data and it becomes so rugged that the sampler gets stuck. Their measurements show it plainly — a single monolithic model’s training quality stalls and then degrades once autocorrelation climbs past 0.8. Chaining 2 to 8 shallow denoising steps instead sidesteps the whole problem, and a closed-loop controller they call the adaptive correlation penalty keeps autocorrelation near zero throughout training.

Binarised Fashion-MNIST, on a 70×70 grid of binary cells with about 12 neighbours each, two-colourable so half the grid updates at once. Training used roughly 1,000 Gibbs iterations per layer; inference used about 250. Most of the larger models used 8 denoising steps.

Energy is simply multiplied out: steps × mixing iterations × cells × energy per cell. With 8 steps, 250 iterations, 70×70 = 4,900 cells and an estimated ~2 femtojoules per cell, you get the TSU figure. The GPU side is FLOPs-per-sample divided by the manufacturer’s quoted FLOPs-per-joule — which the authors note underestimates real GPU energy, so the ratio is if anything conservative. Baselines were VAE, GAN and DDPM.

This is the part worth being precise about. The random number generator circuit is real, characterised in silicon, all-transistor, no exotic components, autocorrelation decaying in about 100 nanoseconds, verified across manufacturing corners. The DTM system itself was not fabricated. The 10,000× rests on a physical energy model plus GPU simulations of the architecture.

Binarising data is not viable in general. There is no reason a convenient hardware wiring pattern should match how real data actually correlates, so naive scaling fails. Only 28×28 greyscale was tested. The largest model tested used ~50,000 cells against ~10⁶ expected on the chip. And they argue DTMs should not run alone at all, but as one component in a hybrid thermodynamic-plus-conventional system — which means a small neural network for embedding, eating into the advantage.